View MTL001_8346043.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

myson technology MTL001 ( rev. 0.95 ) revision 0.95 - 1 - 2000/06/14 xga flat panel controller features general auto configuration of sampling clock frequency, phase, h/v center, as well as white balance. auto detection of present or non-present or over range sync signals and their polarities. composite sync separation and odd/even field detection of interlaced video. on-chip output pll provide clock frequency fine-tune (inverse, duty cycle and delay). selection of serial 2-wire i 2 c or 8-bit direct host interface to 8-bit mcu. 3.3v supplier, 5v i/o tolerance in 256-pin pqfp or 272-pin bga package. input processor single rgb (24-bit) or dual rgb (48-bit) input rates up to 100mhz. support both non-interlaced and interlaced rgb graphic input signals. yuv 4:2:2 or yuv 4:1:1 (ccir601) interlaced video input. glue-less connection to philips saa711x digital video decoder. built-in yuv to rgb color space converter. compliant with digital lv ds/ panellink tmds input interface. pc input resolution up to xga 1024x768 @85hz. video processor independent programmable horizontal and vertical scaling ratios from 1/32 to 32 flexible de-interlacing unit for digital yuv video input data. zoom to full screen resolution of de-interlaced yuv video data stream. built-in programmable gain control for white balance alignments. built-in programmable 8-bit or 10-bit gamma correction table. built-in programmable temporal color dithering. built-in progra mmable interpolation look-up table. support smooth panning under viewing window change. output processor single pixel (18/24-bit) or dual pixel (36/48-bit) per clock digital rgb output. built-in output timing generator with programmable clock and h/v sync. support vga/svga/xga display resolution. overlay input interface with external osd controller. double scan capability for interlaced input. memory interface support 48/ 32/ 24 bit bus width, sdram/sgram x2 or x3 configuration. optional display thr ough internal line buffer without external frame-buffer memory. support power down mode. general description the MTL001 flat panel display (fpd) controller is an input format converter for tft-lcd monitor or lcd tv application which accepts 15-pin d-sub rgb graphic signals (through adc), yuv signals from digital video decoder or digital rgb graphic signals from panellink tmds receiver. it includes a rgb/yuv input processor, configurable frame-buffer memory interface, video scaling up/down processor, osd input interface and output display processor in 256-pin pqfp or 272-pin bga package.
myson technology MTL001 (rev. 0.95) revision 0.95 - 2 - 2000/06/14 block diagram applications this datasheet contains new product information. myson technology reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. yuv input yuv to rgb rgb input scale down frame buffer control ditherin g host interface mode detect auto calibration osd & output mux digital video pc rgb to 8-bit mcu to external osd rgb output to sdram/sgram scale up gain contr ol gamma correct output & memory timing generator MTL001 fpd monitor controller mtv212 8-bit mcu mtv130 osd sdram/ sgram lvds/panellink tmds receiver tft-lcd flat panel digital video decoder adc1 adc2 composite/ s-video d-sub rgb graphic signals
myson technology MTL001 (rev. 0.95) revision 0.95 - 3 - 2000/06/14 1. pin connection note: pin connection of 272-pin bga to be defined later pvss *193 pvss *194 mwe# *195 mcas# *196 mras# *197 dqm1 *198 dqm0 *199 dvss *200 dvdd *201 md7 *202 md6 *203 md5 *204 md4 *205 md3 *206 md2 *207 md1 *208 md0 *209 pvdd *210 md31 *211 md30 *212 md29 *213 md28 *214 md27 *215 md26 *216 md25 *217 md24 *218 pvss *219 ad0 *220 ad1 *221 ad2 *222 ad3 *223 ad4 *224 ad5 *225 ad6 *226 ad7 *227 hcs# *228 pvdd *229 ale *230 pvss *231 hwr# *232 hrd# *233 extmclk *234 rst# *235 bussel *236 irq *237 gpio7 *238 gpio6 *239 gpio5 *240 gpio4 *241 gpio3 *242 gpio2 *243 gpio1 *244 gpio0 *245 extdclk *246 clamp *247 hsync/cs*248 vsync *249 tmdssel *250 tdie/sog*251 pvdd *252 ipclk *253 nc *254 pvss *255 pvss *256 MTL001 (256-pin pqfp) 64* pvdd 63* avdd 62* avdd 61* xi 60* xo 59* avss 58* avss 57* pvss 56* b2in0 55* b2in1 54* b2in2 53* b2in3 52* b2in4 51* b2in5 50* b2in6 49* b2in7 48* pvdd 47* g2in0 46* g2in1 45* g2in2 44* g2in3 43* g2in4 42* g2in5 41* g2in6 40* g2in7 39* pvss 38* r2in0 37* r2in1 36* r2in2 35* r2in3 34* r2in4 33* r2in5 32* r2in6 31* r2in7 30* dvdd 29* rgbsel 28* dvss 27* b1in0 26* b1in1 25* b1in2 24* b1in3 23* b1in4 22* b1in5 21* b1in6 20* b1in7 19* dvdd 18* g1in0/uvin0 17* g1in1/uvin1 16* g1in2/uvin2 15* g1in3/uvun3 14* g1in4/uvin3 13* g1in5/uvun5 12* g1in6/uvun6 11* g1in7/uvin7 10* dvss 9* r1in0/yin0 8* r1in1/yin1 7* r1in2/yin2 6* r1in3/yin3 5* r1in4/yin4 4* r1in5/yin5 3* r1in6/yin6 2* r1in7/yin7 1* pvdd 128* pvss 127* pvss 126* oclk 125* pvdd 124* dden 123* dvsync 122* dhsync 121* dvdd 120* r1out0 119* r1out1 118* r1out2 117* r1out3 116* r1out4 115* r1out5 114* r1out6 113* r1out7 112* dvss 111* g1out0 110* g1out1 109* g1out2 108* g1out3 107* g1out4 106* g1out5 105* g1out6 104* g1out7 103* b1out0 102* b1out1 101* b1out2 100* b1out3 99* b1out4 98* b1out5 97* b1out6 96* b1out7 95* dvss 94* ddclk1 93* ddclk2 92* dvdd 91* r2out0 90* r2out1 89* r2out2 88* r2out3 87* r2out4 86* r2out5 85* r2out6 84* r2out7 83* pvdd 82* g2out0 81* g2out1 80* g2out2 79* g2out3 78* g2out4 77* g2out5 76* g2out6 75* g2out7 74* b2out0 73* b2out1 72* b2out2 71* b2out3 70* b2out4 69* b2out5 68* b2out6 67* b2out7 66* pvss 65* pvss pvdd *129 pvss *130 osdred *131 osdgrn *132 osdblu *133 osden *134 osdint *135 ovsync *136 dvss *137 ohsync *138 dvdd *139 md23 *140 md22 *141 md21 *142 md20 *143 md19 *144 md18 *145 md17 *146 md16 *147 dqm2/ma9 *148 dqm3/ma10 *149 dvss *150 md47 *151 md46 *152 md45 *153 md44 *154 md43 *155 md42 *156 md41 *157 md40 *158 dvdd *159 md15 *160 md14 *161 md13 *162 md12 *163 md11 *164 md10 *165 md9 *166 md8 *167 mcs# *168 dvss *169 md39 *170 md38 *171 md37 *172 md36 *173 md35 *174 md34 *175 md33 *176 md32 *177 mcke *178 dvdd *179 mck *180 pvss *181 ba/ma11 *182 ma8 *183 ma7 *184 ma6 *185 ma5 *186 ma4 *187 ma3 *188 ma2 *189 ma1 *190 ma0 *191 pvdd *192
myson technology MTL001 (rev. 0.95) revision 0.95 - 4 - 2000/06/14 2. pin description adc1 input interface (yuv or rgb or tmds input data) name type pin# description vsync i 249 vertical sync input hsync/cs i 248 horizontal or composite sync input rgbsel o 29 input select. 1:rgb input, 0:yuv input tmdssel o 250 tmds input select, active high clamp o 247 clamp pulse output for adc ipclk i 253 input pixel clock r1in[7:0]/yin[7:0] i 2-9 red or y channel or tmds input data (single/dual adc) g1in[7:0]/uvin[7:0] i 11-18 green or uv channel or tmds input data (single/dual adc) b1in[7:0] i 20-27 blue channel or tmds input data (single/dual adc) tdie i 251 tmds digital input enable adc2 input interface (rgb data) name type pin# description r2in[7:0] i 31-38 red channel input data (dual adc) or control bit for yuv video input bit 4: vphref, video input horizontal reference signal bit 3: vpvs, video input vsync signal bit 2: vpodd, video input odd/even field signal bit 1: vphs, video input hsync signal bit 0: vpclk, video input clock signal g2in[7:0] i 40-47 green channel input data (dual adc) b2in[7:0] i 49-56 blue channel input data (dual adc) display output interface name type pin# description dden o 124 display data output enable for lcd panel dvsync o 123 display vertical sync output dhsync o 122 display horizontal sync output ddclk1 o 94 display output clock for odd data ddclk2 o 93 display output clock for even data r1out[7:0] o 113-120 red output even data , bit[7:2] for 6-bit panel g1out[7:0] o 104-111 green output even data , bit[7:2] for 6-bit panel b1out[7:0] o 96-103 blue output even data , bit[7:2] for 6-bit panel r2out[7:0] o 84-91 red output odd data , bit[7:2] for 6-bit panel g2out[7:0] o 75-82 green output odd data , bit[7:2] for 6-bit panel b2out[7:0] o 67-74 blue output odd data , bit[7:2] for 6-bit panel memory interface name type pin# description mck o 180 memory output clock mcke o 178 memory clock enable mcs# o 168 memory chip select, active low. mras# o 197 memory row address strobe, active low mcas# o 196 memory column address strobe, active low mwe# o 195 memory write enable, active low dqm[1:0] o 198-199 memory data mask byte enable ba/ma11 o 182 memory bank address or memory address line dqm3/ma10 o 149 sgram data mask byte enable or sdram address line dqm2/ma9 o 148 sgram data mask byte enable or sdram address line ma[8:0] o 183-191 memory address line
myson technology MTL001 (rev. 0.95) revision 0.95 - 5 - 2000/06/14 md[47:40] i/o 151-158 memory blue (b1) data md[39:32] i/o 170-177 memory green (g1) data md[31:24] i/o 211-218 memory red (r1) data md[23:16] i/o 140-147 memory blue (b0) data md[15:8] i/o 160-167 memory green (g0) data md[7:0] i/o 202-209 memory red (r0) data host interface name type pin# description rst# i 235 system reset input, active low. ad[7:0] i/o 227-220 the address and data bus of 8-bit direct interface or 2-wire i 2 c series bus bit 1: sda, serial bus data bit 0: sck, serial bus clock hwr# i 232 host write strobe, active low hrd# i 233 host read strobe, active low ale i 230 host address latch enable for 8-bit direct bus hcs# i 228 host chip select bussel i 236 bus mode selection. 0: i 2 c bus, 1: 8-bit direct bus irq o 237 interrupt request output osd interface name type pin# description oclk o 126 clock for external osd ovsync o 136 vertical sync for external osd ohsync o 138 horizontal sync for external osd osdred i 131 osd red input osdgrn i 132 osd green input osdblu i 133 osd blue input osdint i 135 osd intensity input osden i 134 osd overlay enable other interface name type pin# description xi i 61 oscillator frequency input xo o 60 oscillator frequency output extdclk i 246 external display clock input extmclk i 234 external memory clock input gpio[7:0] i/o 238-245 general purpose i/o or bit 7: advs, vertical sync for a/d converter bit 6: adhs, horizontal sync for a/d converter bit 2: ma9_sgram, memory address 9 for sgram bit 0: rawhs/sog, input source hsync or input sync on green default: bit[7:2]: output direction bit[1:0]: input direction nc - 254 no connection 3.3v power and ground name pin# description dvdd 19, 30, 92, 121, 139, 159, 179, 201 digital power 3.3v dvss 10, 28, 95, 112, 137, 150, 169, 200 digital ground pvdd 1, 48, 64, 83, 125, 129, 192, 210, 229, 252 pad power 3.3v pvss 39, 57, 65, 66, 127, 128, 130, 181, 193, 194, pad ground
myson technology MTL001 (rev. 0.95) revision 0.95 - 6 - 2000/06/14 219, 231, 255, 256 avdd 62, 63 analog power 3.3v avss 58, 59 analog ground
myson technology MTL001 (rev. 0.95) revision 0.95 - 7 - 2000/06/14 3. functional description 3.1 input processor general description the function of input interface is to provide the interface between MTL001 and external input devices. it can process both non-interlaced and interlaced rgb graphic input, yuv video input, and digital rgb input compliant with digital lvds/ panellink tmds interface. it also contains the decimation circuit to scale down the input image with arbitrary ratios down to 1/32 and the built-in yuv to rgb color space converter. 3.1.1 rgb input format the rgb input port can work in two modes: single pixel mode (24 bits) and double pixel mode (48 bits). for single pixel mode, only the ports r1in[7:0], g1in[7:0], and b1in[7:0] are internally sampled. for double pixel mode, besides the ports r1in[7:0], g1in[7:0], and b1in[7:0], the ports r2in[7:0], g2in[7:0], and b2in[7:0] are needed additionally. the r/g/b1in ports are sampled at the rising edge of the rgb input clock, and the r/g/b2in ports are sampled at the falling edge. 3.1.2 tmds input format the digital rgb input port works just in the same way as sec 3.1.1 except that pin ? digital input enable dien ? is needed. with a flexible single or double pixel input interface, the supported format is up to true color, including the 18 bit/pixel or 24 bit/pixel in 1 or 2 pixels/clock mode. 3.1.3 yuv input format the yuv input port supports interlaced video data from the most common video decoder ics like saa711x. the 16 bit data bus is shared by ports r1in[7:0] and g1in[7:0]. the 5 bit control signals are shared with the port r2in[4:0]. the 16 bit data is sampled at the rising edge of the shared video clock vpclk when the shared data enable href is active. the supported formats are yuv4 :1:1 and yuv4:2:2 with ccir601 standard. 3.1.4 yuv to rgb converter it is used to convert ycbcr format into rgb format. the basic equations are as follows: r = y + 1.371( cr ? 128) g = y ? 0.698( cr ? 128) ? 0.336( cb ? 128) b = y + 1.732( cb - 128) 3.1.5 de-interlace mode for interlace input, MTL001 features several de-interlacing algorithms for processing interlaced video data depending on the type of input images. static mode in this mode, the first and second fields are simply put together without any filtering. memory for two fields is needed. it is commonly used in still image input. toggle mode in this mode, only one field is displayed at a time. first field and second field is toggling displayed. the missing lines are calculated from duplicating the neighboring lines. for moving picture, it has a good quality. spatial mode in this mode, two fields are toggled displayed, just like toggle mode. the missing lines are calculated from interpolating the neighboring lines. this mode has an generally good quality for still and moving picture. 3.1.6 sync processor the v/h sync processing block performs the functions of composite signal separation/insertion , sync inputs the presence check, frequency counting, polarity detection and control. it contains a de-glitch circuit to filter out any pulse shorter than one osc period which is treated as noise among v/h sync pulses.
myson technology MTL001 (rev. 0.95) revision 0.95 - 8 - 2000/06/14 v/h sync frequency counter MTL001 measures vsync/hsync frequency counted in the proper clock and save the information in register. users can read the figure and calculate vsync/hsync frequency using the following formulae: f vsync = f osc / n vsync 5 1/256 f hsync = f osc / n hsync 5 8 where f vsync : vsync frequency f hsync : hsync frequency f osc : oscillator clock with 14.31818 mhz n vsync : counted number of vsync n hsync : counted number of hsync v/h sync presence check this function checks the input vsync, where vpre flag is set when vsync is over 40hz or cleared when vsync is under 10hz and the input is hsync, where hpre flag is set when hsync is over 10khz or cleared when hsync is under 10hz. v/h polarity detect this function detects the input vsync/hsync high and low pulse duty cycle. if the high pulse duration is longer than that of low pulse, the negative polarity is asserted; otherwise, positive polarity is asserted. composite sync separation/insertion MTL001 continuously monitors the input hsync. if the input vsync can be extracted from it, a cvpre flag is set. MTL001 can insert hsync pulse during composite vsync ? s active time and the insertion frequency can adapt to original hsync ? s. 3.1.7 auto tune auto tune function consists of auto position that automatically centering the screen and auto calibration which contains phase calibration, histogram, min/max value, and pixel grab described as below. with this auto adjustment support it is possible to measure the correct phase, frequency, gain, and offset of adc. the horizontal and vertical back porches of input image and the horizontal and vertical active regions can also be measured. firmware can adjust input image registers automatically by reading auto tune ? s registers in single or burst mode. auto position MTL001 provides horizontal/vertical back porch and active region values. users can use these values to set input sample registers to aid in centering the screen automatically. phase calibration MTL001 provides auto calibration registers to measure the quality of current adc ? s phase and frequency. the biggest auto calibration registers value means the right value of adc ? s phase and frequency. MTL001 has two kinds of algorithms to calculate auto calibration ? s value. one is the traditional difference method, the other is myson ? s proprietary method; the latter one is recommended for a better performance. histogram histogram means the total number of input pixels below/above one threshold value, for individual r/g/b colors. this advanced function helps the firmware to analyze adc performance. usually the firmware can use this information to measure adc ? s noise margin, and adjust its offset and gain, or even aid in the mode detection. min/max value min/max value means minimum or maximum pixel value within the specified input active image region for each rgb channel. this information is usually used to adjust adc ? s offset and gain. pixel grab pixel grab means users can grab a single input pixel at any one point. the position of the point can be programmed by users. this is another traditional method to measure adc ? s phase and frequency.
myson technology MTL001 (rev. 0.95) revision 0.95 - 9 - 2000/06/14 3.2 video processor general description MTL001 possesses a powerful and programmable video processor by providing the following functions: scaling up/down, gain control, brightness control, gamma correction, and dithering control. the block diagram of video processor is as follows: fig. 3.2.1 video processor block diagram 3.2.1 scaling MTL001 provides scaling function ranging from 1/32 to 32 for both up and down scaling, and for both horizontal and vertical processing. note that the up and down scaling cannot operate in the same time, because they share the same line buffers. for scaling up, both horizontal and vertical processing, MTL001 provides four methods: pass mode : image will be passed through without considering any scaling factor. duplicate mode : image will be scaled up/down based on scaling factor. every point of output image comes from the input. in this method, output image will have the good contrast but may be non- uniformed. bilinear mode : image will be scaled up/down based on scaling factor. every point of output image data will be filtered by bilinear filter. in this method, output image will have the good scaling quality but may be blurred. interpolation table mode : image will be scaled up/down based on scaling factor. every point of output image data will be filtered by the user defined filter. gain brightness gamma dithering scaling transition table scaling factor brightness factor gamma table gain factor dithering table
myson technology MTL001 (rev. 0.95) revision 0.95 - 10 - 2000/06/14 fig. 3.2.2 scaling filter note: for scaling down, for both horizontal and vertical processing, MTL001 provides three methods: pass mode, duplicate mode, and bilinear mode. 3.2.2 gain/brightness control MTL001 provides gain and brightness control to adjust the contrast and brightness of output color by programming the gain and brightness coefficients. this adjustment is applied to rgb colors individually. auto-white balance can be achieved by using this function. 3.2.3 gamma correction gamma correction is used to compensate the non-linearity of lcd display panel. MTL001 contains an 8/10- bit gamma table to fix this phenomenon. the 10-bit gamma table performs a better output quality, and is commonly used together with dithering function. a traditional 8-bit gamma correction table can also be used. 3.2.4 color dithering MTL001 supports true color (8 bits per color) or high color (6 bits per color) display. in the latter case, users can turn on dithering function to avoid artificial contour due to truncation. the dithering function works in two modes: static dithering: dithering coefficient is fixed. temporal dithering: dithering coefficient is time dependent. interpolation pixel input pixel a b o 64 sc 32 63 32 63 sc sc ? o = [(64-sc ? )*a + sc ? *b]/64 [a] [b] [c] [a]: duplicate filter [b]: bilinear filter [c]: user defined filter
myson technology MTL001 (rev. 0.95) revision 0.95 - 11 - 2000/06/14 3.3 output processor general description output processor provides the interface for both lcd panel and osd controller. MTL001 can work for frame- buffer or non-frame-buffer mode. when in frame-buffer mode, there is no restriction between the timing of input and output. when in non-frame-butter mode, output frame rate must be equal to input frame rate and output display time must be equal to input display time due to the absence of frame buffer. some features based on using the frame buffer do not work in non-frame-buffer mode, for example the screen write, static mode in de-interlace etc. 3.3.1 display timin g generation there are three display timing modes: frame - b uffer mode : is used for frame rate conversion. external frame buffer is needed. non-frame-buffer mode : performs a low cost version of solution where the external frame buffer is not needed. this mode is used in the condition that output frame rate is equal to input frame; some features are disabled in this mode. frame sync mode : is used for video input. in this mode, output frame is synchronized to input frame, gives the moving picture a smooth change. fig. 3.2.3 display timing modes external frame buffer external frame buffer input frame input frame input frame output frame output frame output frame x x lock point lock point frame buffer mode: non frame buffer mode frame sync mode
myson technology MTL001 (rev. 0.95) revision 0.95 - 12 - 2000/06/14 3.3.2 osd overlay MTL001 allows the integration of overlay data with the scaled output pixel stream. it provides a fully compatible osd interface. individual osd clock, osd hsync and osd vsync are sent to external osd device. mtl003 receives osd enable, osd red, osd green, osd blue, and osd intensity from external osd device. 3.3.3 rgb output format MTL001 output interface consists of two pixel ports, each containing red, green, and blue color information with a resolution of 6/8 bits per color. these two ports are port1 and port2 respectively . the control signals for output port are the display horizontal sync signal (dhsync) , the display vertical sync signal (dvsync) and the display data enable signal (dden). all the signals mentioned above are synchronous to the output clock. the output timing relative to the active edge of the output clock is programmable. there are two rgb output formats: single pixel mode is designed to support tft panels with single pixel input. only port1 is active. the frequency of dclk1 is equal to the internal display clock. dual pixel mode is designed to support tft panels with dual pixel input. port1 and port2 are used. the first pixel is at port1, and the second at port2. dclk dden r1out/g1out /b1out 000 rgb0 rgb1 rgb2 rgb3 rgb4 dclk1 dden dclk2 dclk r1out/g1out /b1out 000 rgb0 rgb2 rgb4 rgb6 rgb8 r2out/g2out /b2out 000 rgb1 rgb3 rgb5 rgb7 rgb9 single port dual port fig. 3.2.4 display data timing
myson technology MTL001 (rev. 0.95) revision 0.95 - 13 - 2000/06/14 3.4 memory interface general description in frame buffer mode, the MTL001 connects to the external frame buffers by means of memory interface. the external frame memory can be made for 1m 5 16bits sdram , 256k 5 32bits or 512 k 5 32bits sgram device s . due to different applications such as vga, svga, xga as well as sxga, the image resolution of input and output will be limited result ing from the bandwidth of memory interface. t wo configurations with 24 , 32 and 48 bits bus modes will be supported to resolve the bandwidth constraint in most of applications. the clock for external frame memory devices can be provided from the internal pll circuit or the external clock applied to pin extmclk and its frequency can be up to 1 18 mhz. the MTL001 also supplies a simple and complete memory self-testing mechanism for sdram and sgram, which can be used to detect memory cell status and to check connection in memory interface. 3.4.1 sdram configuration in current applications, t he most popular arrangement of sdr am is 1m 5 16bits. to achieve the desired bandwidth in memory interface, 2 or 3 devices are constructed in parallel. the memory clock ranging from 50mhz to 118mhz is tuned by giving appropriate parameters for the internal pll circuit. in two devices configuration, the 24 and 32 bits bus modes are supported. in three devices, the 48 bits bus mode is supported. in 24 bits bus mode , the maximum supported input image resolution is up to 1024 5 768 @ 60hz. in 32 and 48 bits bus mode, the maximum supported input image resolution is up to 1024 5 768 @ 85hz. table 3.4.1 gives the configuration for different input and output image format. figure 3.4.1 shows the connection between the MTL001 and sdram devices in 2 configurations. unit: device output resolution input resolution svga xga yuv 2 2 vga (640 5 480) 2 2 svga (800 5 600) 2 2 xga (1024 5 768) 2 2 table 3.4.1 sdram configuration in different input and output modes 3.4.2 sgram configuration the sgram devices in 256k 5 32bits and 512k 5 32bits construction s are usually used to feature the wide data bus for high speed applications. in case of sgram usage, the 32 bits data bus of each device is divided into 2 parts to store input image data. the memory clock is adjustable to achieve the desired range of performance like the sdram case above. the maximum supported input image resolution in 24 bits bus mode (2 devices) is up to 800 5 600 @ 85hz, and both the 32 bits bus mode (2 devices) and the 48 bits bus mode (3 devices) can support maximum input image resolution up to 1024 5 768 @ 85hz. table 3.4.2 provides the configuration for different input and output image format. figure 3.4.2 and 3.4. 3 show the connection between the MTL001 and sgram devices in 2 configurations by 256 k 5 32bits and 512 k 5 32bits constructions respectively . unit: device output resolution input resolution svga xga yuv 2 2 vga (640 5 480) 2 2 svga (800 5 600) 2 2 xga (1024 5 768) (512kx32 bits / 256kx32 bits) 2 / 3 2 / 3 table 3.4.2 sgram configurations in different input and output modes
myson technology MTL001 (rev. 0.95) revision 0.95 - 14 - 2000/06/14 fig. 3.4.1 the interface between MTL001 and 1mx16 bits sdram dq7~0 dq15~8 a8~0 ldqm udqm /cs /ras /cas cke /we mcke mcs # mras# mcas# mwe# dqm0 dqm1 ma[8:0] sdram(1m 5 16bits) 5 2 clk mck md[7:0] md[31:24] a10 ba a9 dqm2/ma9 dqm3/ma10 ba/ma11 dq7~0 dq15~8 a8~0 ldqm udqm /cs /ras /cas cke /we clk a10 ba a9 mcke mcs # # mras# mcas# mwe# dqm0 dqm1 ma[8:0] mck dqm2/ma9 dqm3/ma10 ba/ma11 md[15:8] md[39:32] sdram(1m 5 16bits) 5 3 dq7~0 dq15~8 a8~0 ldqm udqm /cs /ras /cas cke /we mcke mcs# mras# mcas# mwe# dqm0 dqm1 ma[8:0] clk mck md[7:0] md[31:24] a10 ba a9 dqm2/ma9 dqm3/ma10 ba/ma11 dq7~0 dq15~8 a8~0 ldqm udqm /cs /ras /cas cke /we clk a10 ba a9 mcke mcs# mras# mcas# mwe# dqm0 dqm1 ma[8:0] mck dqm2/ma9 dqm3/ma10 ba/ma11 md[15:8] md[39:32] dq7~0 dq15~8 a8~0 ldqm udqm /cs /ras /cas cke /we clk a10 ba a9 mcke mcs# mras# mcas# mwe# dqm0 dqm1 ma[8:0] mck dqm2/ma9 dqm3/ma10 ba/ma11 md[23:16] md[47:40]
myson technology MTL001 (rev. 0.95) revision 0.95 - 15 - 2000/06/14 fig. 3.4.2 the interface between MTL001 and 256kx32 bits sgram sgram(128k 5 32bits 5 2 ) 5 3 a8~0 dqm0 dqm1 /cs /ras /cas cke /we mcke mcs# mras# mcas# mwe# dqm0 dqm1 ma[8:0] dqm2 dqm3 dqm2/ma9 dqm3/ma10 dsf ba/ma11 a9(ba) clk mck md[7:0] md[31:24] dq7~0 dq15~8 dq23~16 dq31~24 a8~0 dqm0 dqm1 /cs /ras /cas cke /we dqm2 dqm3 a9(ba) clk dq7~0 dq15~8 dq23~16 dq31~24 dsf mcke mcs# mras# mcas# mwe# dqm0 dqm1 ma[8:0] dqm2/ma9 dqm3/ma10 ba/ma11 mck md[15:8] md[39:32] dsf mcke mcs# mras# mcas# mwe# dqm0 dqm1 ma[8:0] dqm2/ma9 dqm3/ma10 ba/ma11 mck a8~0 dqm0 dqm1 /cs /ras /cas cke /we dqm2 dqm3 a9(ba) clk dq7~0 dq15~8 dq23~16 dq31~24 md[23:16] md[47:40] a8~0 dqm0 dqm1 /cs /ras /cas cke /we mcke mcs# mras# mcas# mwe# dqm0 dqm1 ma[8:0] dqm2 dqm3 dqm2/ma9 dqm3/ma10 dsf ba/ma11 a9(ba) clk mck md[7:0] md[31:24] sgram(128k 5 32bits 5 2 ) 5 2 dq7~0 dq15~8 dq23~16 dq31~24 a8~0 dqm0 dqm1 /cs /ras /cas cke /we dqm2 dqm3 a9(ba) clk dq7~0 dq15~8 dq23~16 dq31~24 dsf mcke mcs# mras# mcas# mwe# dqm0 dqm1 ma[8:0] dqm2/ma9 dqm3/ma10 ba/ma11 mck md[15:8] md[39:32]
myson technology MTL001 (rev. 0.95) revision 0.95 - 16 - 2000/06/14 a 8 ~0 dqm0 dqm1 /cs /ras /cas cke /we mcke mcs# mras# mcas# mwe# dqm0 dqm1 ma[8:0] dqm2 dqm3 dqm2/ma9 dqm3/ma10 dsf ba/ma11 a 10 (ba) clk mck md[7:0] md[31:24] sgram( 256 k 5 32bits 5 2 ) 5 2 dq7~0 dq15~8 dq23~16 dq31~24 gpio [2] a9 a 8 ~0 dqm0 dqm1 /cs /ras /cas cke /we mcke mcs# mras# mcas# mwe# dqm0 dqm1 ma[8:0] dqm2 dqm3 dqm2/ma9 dqm3/ma10 dsf ba/ma11 a 10 (ba) clk mck md[15:8] md[39:32] dq7~0 dq15~8 dq23~16 dq31~24 gpio [2] a9 sgram( 256 k 5 32bits 5 2 ) 5 3 a 8 ~0 dqm0 dqm1 /cs /ras /cas cke /we mcke mcs# mras# mcas# mwe# dqm0 dqm1 ma[8:0] dqm2 dqm3 dqm2/ma9 dqm3/ma10 dsf ba/ma11 a 10 (ba) clk mck md[7:0] md[31:24] dq7~0 dq15~8 dq23~16 dq31~24 gpio [2] a9 a 8 ~0 dqm0 dqm1 /cs /ras /cas cke /we mcke mcs# mras# mcas# mwe# dqm0 dqm1 ma[8:0] dqm2 dqm3 dqm2/ma9 dqm3/ma10 dsf ba/ma11 a 10 (ba) clk mck md[15:8] md[39:32] dq7~0 dq15~8 dq23~16 dq31~24 gpio [2] a9 a 8 ~0 dqm0 dqm1 /cs /ras /cas cke /we mcke mcs# mras# mcas# mwe# dqm0 dqm1 ma[8:0] dqm2 dqm3 dqm2/ma9 dqm3/ma10 dsf ba/ma11 a 10 (ba) clk mck md[23:16] md[47:40] dq7~0 dq15~8 dq23~16 dq31~24 gpio [2] a9 fig. 3.4.3 the interface between MTL001 and 512kx32 bits sgram
myson technology MTL001 (rev. 0.95) revision 0.95 - 17 - 2000/06/14 3.5 host interface general description the primary function of host interface is to provide the interface between MTL001 and external cpu by 2- wire i 2 c bus or direct bus selected by the input pin bussel. it can generate all the i/o decoded control timing to control all the registers in MTL001. the other function is screen write, which allows users to clear frame buffer, and display output as well. 3.5.1 i 2 c serial bus the i 2 c serial interface uses 2 wires, sck (clock) and sda(data i/o) respectively. the sck is used as the sampling clock and sda is a bi-directional signal for the data. the communication must be started with a valid start condition, concluded with stop condition and acknowledged by ack condition by the receiver. the i 2 c bus device address of MTL001 is 0111010x. ad[0] sck, serial bus clock. ad[1] sda, bi-directional serial bus data. the start condition means a high to low transition of sda when sck is high , the stop condition means a low to high transition of sda when sck is high. and data of sda can only change when sck is low. ref. fig.3.5.1. fig. 3.5.1 start, stop ,and data definition the i 2 c interface supports random write, sequential write, current address read, random read and sequential read operations. random write for random write operation, it contains the slave address with r/w bit set to 0 and the word address which is comprised of 8 bits that provides the access to any one of the 256 bytes in the selected memory range. upon receipt of the word address, mtl003 responds with an acknowledge and waits for the next eight bits of data again, responding with an acknowledge, and then the master generates a stop condition. ref. fig.3.5.2. sda sck start data change data change stop
myson technology MTL001 (rev. 0.95) revision 0.95 - 18 - 2000/06/14 fig. 3.5.2 random write sequential write the initial step of sequential write is the same as random write, after the receipt of each word data, MTL001 will respond with an acknowledge and then internal address counter will increment by one for next data write. if the master stops writing data, it will generate stop condition. ref. fig. 3.5.3. fig. 3.5.3 sequential write current address read MTL001 contains an address counter which maintains the last access address incremented by one. if the last access address is n, the read data should access from address n+1. upon receipt of the slave address with r/w bit set to 1, MTL001 generates an acknowledge and transmits the eight bits data. after receiving data the master will generate a stop condition instead of an acknowledge. ref. fig. 3.5.4. fig. 3.5.4 current address read s t a r t a c k slave address data r sda s t o p s t a r t a c k a c k a c k s t o p slave address word address data w sda sda s t a r t a c k a c k a c k slave address word address data n w data n+1 s t o p a c k a c k data n+x
myson technology MTL001 (rev. 0.95) revision 0.95 - 19 - 2000/06/14 random read the operation of random read allows access to any address. before the reading data operation, it must issue a ? dummy write ? operation ? the master issues the start condition, slave address and then the word address it is to read. after the word address acknowledge, the master generating a start condition again and slave address with r/w bit is set to 1. MTL001 then transmits the 8 bits of data. upon the completion of receiving data, the master will generate a stop condition instead of an acknowledge. ref. fig 3.5.5. fig. 3.5.5 random read sequential read the initial step can be as either current address read or random read. the first read data is transmitted in the same manner as other read methods. however, the master generates an acknowledge indicating that it requires more data to read. MTL001 continues to output data for each acknowledge received. the output data is sequential and the internal address counter increments by one for next read data. ref. fig. 3.5.6. fig. 3.5.6 sequential read 3.5.2 8-bit direct bus the direct bus use ad[7:0], hwr#, hrd#, ale, hcs# as the interface with host. ale is used to latch read or write address from ad[7:0] and hrd#, hwr# to access data. ref. fig. 3.5.7. ad[7:0] address and data multiplex bus. hrd# cpu read data strobe, active low. hwr# cpu write data strobe, active low. ale ale =1 latch read or write address, ale=0 represents i/o data. hcs# enable signal for cpu access, active low. s t a r t a c k a c k a c k slave address word address w sda s t a r t slave address r data s t o p s t a r t a c k slave address data n r sda data n+1 a c k a c k data n+x s t o p
myson technology MTL001 (rev. 0.95) revision 0.95 - 20 - 2000/06/14 fig. 3.5.7 direct bus timing 3.5.3 interrupt MTL001 supports one interrupt output signal (irq) which can be programmed to provide sync related or function status related interrupts to the system. upon receiving the interrupt request, firmware needs to firstly check the interrupt event by reading the interrupt flag control registers (reg. e8h and e9h) to decide what events are happening. after the operation is completed, firmware needs to clear interrupt status by writing the same registers reg. e8h and e9h. furthermore, by using the interrupt flag enable registers (reg. eah and ebh), each interrupt event can be masked. 3.5.4 screen write screen write function can be used to clear frame buffer memory and display output by a fixed value defined in reg. c6h, c7h, c8h. 3.5.5 bi-direc tional gpio MTL001 supports eight general purpose input and output (gpio) pins gpio[7:0] on chip. the gpio[5:0] pins are bi-directional gpio pins, and the gpio[7:6] pins are output only gpio pins. there are two functions for gpio[7:6] pins. one is to set them as output only gpio pins, and the other is to set them as composite decoded vsync/hsync for a/d converters in vga input path. the data and i/o direction of gpio[7:0] pins are controlled by reg. f4h and f5h respectively, and each bit in the register is mapped to gpio[7:0] correspondingly. the following description is the process to control gpio[0] and gpio[6] in detail, and the control processes of gpio[4:1] and gpio[7] also follows in the same manner. bi-directional gpio control process q setting reg. f5h/d0 = 0 or 1 to assign gpio[0] as output or input. q writing data to reg. f4h/d0 when gpio[0] is assigned to output status, otherwise reading data from reg. f4h/d0 when gpio[0] is input. output only gpio control process q setting reg. f5h/d6 = 0 or 1 to assign gpio[6] as output or tri-state. q setting reg. f6h/d0 = 0 to select output source from reg. f4h/d6 or setting it as 1 to make gpio[6] pin to output adhs which is hsync signal decoded from vga input composite signal by the MTL001. q writing data to f4h/d6 when gpio[6] is assigned to output only gpio pin, that is, f6h/d0 = 0 and f5h/d6 = 0. if f6h/d0 is set to 1, the gpio[6] pin outputs adhs for ad converters in vga input path. 3.5.6 update register contents i/o write operation to some consecutive register set can have the ? double buffer ? effect by setting the reg. c1h/d4. written data is first stored in an intermediate bank of latches and then transferred to the active register set by setting reg. c1h/d1-0. ad[7:0] data address ale hwr/hrd
myson technology MTL001 (rev. 0.95) revision 0.95 - 21 - 2000/06/14 3.6 on-chip pll general description the MTL001 needs three clock sources to drive synchronous circuits on chip. these clocks are generated from the internal phase lock loop (pll) circuits with reference to the oscillator clock which is applied to pin xi and xo by an external quartz crystal at 14.31818 mhz. first one is the same as to the oscillator clock at frequency (14.31818 mhz) to detect and measure graphic vertical and horizontal sync frequency, polarity as well as presence. the second is memory clock to synchronize memory controller with the external frame buffers. the third is the display clock for display controller on chip and output signals to lcd panel. 3.6.1 reference clock it is the counting basis of counter values in sync processor such as vs and hs period count registers; that is, the read back values from these registers must multiply the period of this clock to estimate vs and hs frequency. incorporating with polarity and frequency information of vs and hs, it can show the input graphic image mode and pixel clock frequency. 3.6.2 memory clock this clock is the synchronous clock for the external frame buffer. depending on the bandwidth needed by the applications, dram types and configurations, the memory clock changes from 50 mhz to 118 mhz by means of adjusting a set of appropriate values for m, n as well as r. the formula for calculating the desired frequency of memory clock is as follows: f mclk = f osc 5 (m+2)/(n+2) 5 1/r where f mclk : the desired memory clock f osc : oscillator clock with 14.31818 mhz m : post-divider ratio n : pre-divider ratio r : optional divider ratio 3.6.3 display clock this clock is the synchronous clock for lcd panel. according to the lcd panel resolution of applications, the display clock range is from 50 mhz to 100 mhz by means of choosing a set of appropriate values for m, n as well as r. the computing formula is exactly the same as for the memory clock.
myson technology MTL001 (rev. 0.95) revision 0.95 - 22 - 2000/06/14 4. register description input control registers address mode registers reset value 00h r/w input image vertical active line start - low 00h 01h r/w input image vertical active line start - high 00h 02h r/w input image vertical active lines - low 00h 03h r/w input image vertical active lines - high 00h 04h r/w input image horizontal active pixel start - low 00h 05h r/w input image horizontal active pixel start - high 00h 06h r/w input image horizontal active pixels - low 00h 07h r/w input image horizontal active pixels - high 00h 10h r/w input image control register 0 00h 11h r/w input image control register 1 00h 12h r/w input image control register 2 00h 13h r/w input image control register 3 00h 14h r/w input image control register 4 00h 15h r/w input image control register 5 00h 16h r/w input image control register 6 00h 1ah r/w input delay control 2 00h 1ch r/w hs1 sample window forward extend 00h 1dh r/w hs1 sample window backward extend 00h 1fh ro input image status register - 20h r/w input image back porch guard band 00h 21h r/w input image front porch guard band 00h frame sync registers address mode registers reset value 28h r/w frame sync control 00h 2ch r/w input image vertical lock position - low 00h 2dh r/w input image vertical lock position - high 00h 2eh r/w input image horizontal lock position - low 00h 2fh r/w input image horizontal lock position - high 00h auto calibration registers address mode registers reset value 30h r/w auto calibration control 0 80h 31h r/w auto calibration control 1 00h 34h ro auto calibration red value - byte 0 - 35h ro auto calibration red value - byte 1 - 36h ro auto calibration red value - byte 2 - 37h ro auto calibration red value - byte 3 - 38h ro auto calibration green value - byte 0 - 39h ro auto calibration green value - byte 1 - 3ah ro auto calibration green value - byte 2 - 3bh ro auto calibration green value - byte 3 - 3ch ro auto calibration blue value - byte 0 - 3dh ro auto calibration blue value - byte 1 - 3eh ro auto calibration blue value - byte 2 - 3fh ro auto calibration blue value - byte 3 -
myson technology MTL001 (rev. 0.95) revision 0.95 - 23 - 2000/06/14 40h r/w pixel grab v reference position - low 00h 41h r/w pixel grab v reference position - high 00h 42h r/w pixel grab h reference position - low 00h 43h r/w pixel grab h reference position - high 00h 44h r/w histogram reference color - red 00h 45h r/w histogram reference color - green 00h 46h r/w histogram reference color - blue 00h sync processor registers address mode registers reset value 48h r/w sync processor control 00h 49h r/w auto position control 00h 4ah r/w auto position reference color - red 00h 4bh r/w auto position reference color - green 00h 4ch r/w auto position reference color - blue 00h 4eh r/w clamp pulse control 0 00h 4fh r/w clamp pulse control 1 00h 50h ro input vs period count by refclk - low - 51h ro input vs period count by refclk - high - 52h ro input v back porch count by input hs - low - 53h ro input v back porch count by input hs - high - 54h ro input v active lines count by input hs - low - 55h ro input v active lines count by input hs - high - 56h ro input v total lines count by input hs - low - 57h ro input v total lines count by input hs - high - 58h ro input hs period count by refclk - low - 59h ro input hs period count by refclk - high - 5ah ro input h back porch count by input pixel clock - low - 5bh ro input h back porch count by input pixel clock - high - 5ch ro input h active pixels count by input pixel clock - low - 5dh ro input h active pixels count by input pixel clock - high - 5eh ro input h total pixels count by input pixel clock - low - 5fh ro input h total pixels count by input pixel clock - high - display control registers address mode registers reset value 60h r/w display vertical total - low 00h 61h r/w display vertical total - high 00h 62h r/w display vertical sync end- low 00h 63h r/w display vertical sync end - high 00h 64h r/w display vertical active start - low 00h 65h r/w display vertical active start - high 00h 66h r/w display vertical active end - low 00h 67h r/w display vertical active end - high 00h 68h r/w display vertical border start - low 00h 69h r/w display vertical border start - high 00h 6ah r/w display vertical border end - low 00h 6bh r/w display vertical border end - high 00h 70h r/w display horizontal total - low 00h
myson technology MTL001 (rev. 0.95) revision 0.95 - 24 - 2000/06/14 71h r/w display horizontal total - high 00h 72h r/w display horizontal sync end - low 00h 73h r/w display horizontal sync end - high 00h 74h r/w display horizontal active start - low 00h 75h r/w display horizontal active start - high 00h 76h r/w display horizontal active end - low 00h 77h r/w display horizontal active end - high 00h 78h r/w display horizontal border start - low 00h 79h r/w display horizontal border start - high 00h 7ah r/w display horizontal border end - low 00h 7bh r/w display horizontal border end - high 00h 88h r/w output image control register 0 00h 89h r/w output image control register 1 00h 8ah r/w output image control register 2 00h 90h r/w color gain control - red 80h 91h r/w color gain control - green 80h 92h r/w color gain control - blue 80h 93h r/w brightness control - red 00h 94h r/w brightness control - green 00h 95h r/w brightness control - blue 00h 96h r/w border window color - red 00h 97h r/w border window color - green 00h 98h r/w border window color - blue 00h 9eh r/w dithering table data port - 9fh r/w gamma table data port - a0h r/w osd control register 0 08h a1h r/w osd control register 1 00h a2h r/w osd control register 2 00h a4h r/w output invert control 00h a5h r/w output tri-state control 00h a6h r/w output clocks delay adjustment 00h a7h r/w output clocks duty cycle adjustment 00h a9h r/w output miscellaneous control 00h aah r/w output vertical line number - low ffh abh r/w output vertical line number - high 02h ach ro output horizontal total pixel number ? low - adh ro output horizontal total pixel number ? high - aeh ro output horizontal total residue number ? low - afh ro output horizontal total residue number - high - zoom control registers address mode registers reset value b0h r/w zoom control register 0 00h b1h r/w zoom control register 1 00h b2h r/w zoom vertical scale down integer 00h b3h r/w zoom horizontal scale down integer 00h b4h r/w zoom vertical scale ratio - low 00h b5h r/w zoom vertical scale ratio - high 00h b6h r/w zoom horizontal scale ratio - low 00h b7h r/w zoom horizontal scale ratio - high 00h
myson technology MTL001 (rev. 0.95) revision 0.95 - 25 - 2000/06/14 bfh r/w interpolation table data port - host control registers address mode registers reset value c0h r/w host control register 0 00h c1h r/w host control register 1 00h c4h r/w host screen write line length - low 00h c5h r/w host screen write line length - high 03h c6h r/w host fill color - red 00h c7h r/w host fill color - green 00h c8h r/w host fill color - blue 00h cbh ro host access mode status - memory control registers address mode registers reset value d0h r/w memory type control 00h d2h r/w memory self test control 00h d4h r/w memory line offset - low 00h d5h r/w memory line offset - high 04h dbh ro memory self-test compare error address - low - dch ro memory self-test compare error address - middle - ddh ro memory self-test compare error address - high - clock control registers address mode registers reset value e0h r/w clock control register 00h e1h wo clock synthesizer value load - e2h r/w display clock synthesizer n value 0bh e3h r/w display clock synthesizer m value 32h e4h r/w memory clock synthesizer n value 0bh e5h r/w memory clock synthesizer m value 32h e6h r/w clock synthesizer r value 00h interrupt control registers address mode registers reset value e8h r/w sync interrupt flag control 00h e9h r/w general interrupt flag control 00h eah r/w sync interrupt enable 00h ebh r/w general interrupt enable 00h ech r/w hs frequency change interrupt compare 00h miscellaneous registers address mode registers reset value f1h r/w power management control 00h f4h r/w gpio control register 00h f5h r/w gpio direction control 00h f6h r/w gpio misc control 00h input image vertical active line start - low (address 00h) (r/w) it defines the low byte of the start position of the vertical active window.
myson technology MTL001 (rev. 0.95) revision 0.95 - 26 - 2000/06/14 d7-0 iv_act_ start[7:0] input image vertical active line start - high (address 01h) (r/w) it defines the high byte of the start position of the vertical active window. d7-3 reserved d2-0 iv_act_ start[10:8] input image vertical active lines - low (address 02h) (r/w) it defines the low byte of the number of active lines of the vertical active window. d7-0 iv_act_ len[7:0] input image vertical active lines - high (address 03h) (r/w) it defines the high byte of the number of active lines of the vertical active window. d7-3 reserved d2-0 iv_act_ len[10:8] input image horizontal active pixel start - low (address 04h) (r/w) it defines the low byte of the start position of the horizontal active window. d7-0 ih_act_ start[7:0] input image horizontal active pixel start - high (address 05h) (r/w) it defines the high byte of the start position of the horizontal active window. d7-3 reserved d2-0 ih_act_ start[10:8] input image horizontal active pixels - low (address 06h) (r/w) it defines the low byte of the number of active pixels of the horizontal active window. d7-0 ih_act_ width[7:0] input image horizontal active pixels - high (address 07h) (r/w) it defines the high byte of the number of active pixels of the horizontal active window. d7-3 reserved d2-0 ih_act_ width[10:8] input image control register 0 (address 10h) (r/w) d7 horizontal sampling point reference 0: from input hsync.
myson technology MTL001 (rev. 0.95) revision 0.95 - 27 - 2000/06/14 1: from input href (only for v ideo decoder). d6 input ycbcr format 0: 4-2-2 1: 4-1-1 d5 digital rgb 6 bit mode 0: 8 bits 1: 6 bits d4 digital rgb mode select 0: rgb input from adc 1: rgb input from panel link d3 input image format 0: rgb888 1: ycbcr d2 input clock source 0: from graphic pll clock. 1: from video decoder clock. d1 input image source 0: from graphic source through adc. 1: from video source through video decoder like saa7111a. d0 adc configuration 0: double pixel mode 1: single pi xel mode input image control register 1 (address 11h) (r/w) d7 reserved d6-4 de-interlace mode select 000: all fields write mode 001: toggle field write mode 010: spatial filtering write mode d3 input yuv ccir656 format 0: disable 1: enable d2-1 reserved d0 still mode enable 0: live mode 1: still mode input image control register 2 (address 12h) (r/w) d7 input odd field invert 0: normal 1: invert d6 external input interlace select 0: non-interlace
myson technology MTL001 (rev. 0.95) revision 0.95 - 28 - 2000/06/14 1: interlace d5 external input vsync polarity 0: active low 1: active high d4 external input hsync polarity 0: active low 1: active high d3 input odd field source 0: from internal detection 1: from external pin. d2 input interlace source 0: from internal detection 1: from register setting (d6) d1 input vsync polarity source 0: from internal detection 1: from register setting (d5) d0 input hsync polarity source 0: from internal detection 1: from register setting (d4) input image control register 3 (address 13h) (r/w) d7 active position area for auto position in tmds 0: from internal detection 1: from external data enable (tdie) d6-3 reserved d2 sync on green select 0: select normal hsync/ composite sync 1: select sy nc on green d1 input vertical timing based on vsync 0: leading edge 1: trailing edge d0 input horizontal timing based on hsync 0: leading edge 1: trailing edge input image control register 4 (address 14h) (r/w) d7 input odd field detecti on point 0: at the start of vsync pulse. 1: at the end of vsync pulse. d6 input image port a, b data and clocks swap 0: normal 1: swap d5 reserved
myson technology MTL001 (rev. 0.95) revision 0.95 - 29 - 2000/06/14 d4 input image cbcr order swap 0: normal 1: swap d3-0 reserved input image control register 5 (address 15h) (r/w) d7 horizontal pixel valid select 0: from internal programming 1: from external href/tdie d6-0 reserved input image control register 6 (address 16h) (r/w) d7-3 reserved d2 adc hs polarity invert when d1=1 0: ac tive low 1: active high d1 raw hs path enable 0: disable 1: enable d0 reserved input delay control 2 (address 1ah) (r/w) d7-4 input vsync delay adjustment 1111: 7 idclks delay 1110: 6 idclks delay 1101: 5 idclks delay 1100: 4 idclks delay 1011: 3 idclks delay 1010: 2 idclks delay 1001: 1 idclk delay 1000: reserved 0111: 7ns gate delay 0110: 6ns gate delay 0101: 5ns gate delay 0100: 4ns gate delay 0011: 3ns gate delay 0010: 2ns gate delay 0001: 1ns gate dela y 0000: no delay d3-0 input hsync delay adjustment 16 steps to change, each of them is 1ns delay/step. input hs pulse width forward extend (address 1ch) (r/w) d7-0 input hs pulse width forward extend by idclk hs1fwext[7:0]: used when interlace first/second field detection.
myson technology MTL001 (rev. 0.95) revision 0.95 - 30 - 2000/06/14 input hs pulse width backward extend (address 1dh) (r/w) d7-0 input hs pulse width backward extend by idclk hs1bwext[7:0]: used when interlace first/second field detection. input image status register (address 1fh) (ro) d7 display vsync monitor show display vsync signal directly. d6 input vsync monitor show input vsync signal directly. d5 external input interlace status 0: non-interlace 1: interlace d4 extracted cvsync present status 0: not presen t 1: present d3 external input vsync present status 0: not present 1: present d2 external input hsync present status 0: not present 1: present d1 external input vsync polarity status 0: active low 1: active high d0 external input hsyn c polarity status 0: active low 1: active high input image back porch guard band (address 20h) (r/w) d7-0 input image back porch guard band by idclk hbpgb[7:0]: used in auto position detection to mask out unwanted data. input image front porch guard band (address 21h) (r/w) d7-0 input image front porch guard band by idclk hfpgb[7:0]: used in auto position detection to mask out unwanted data. frame sync control 0 (address 28h) (r/w) d7-5 reserved d1 frame sync select in frame buffer mode 0: normal 1: frame sync d0 frame buffer mode select 0: frame buffer mode
myson technology MTL001 (rev. 0.95) revision 0.95 - 31 - 2000/06/14 1: non frame buffer mode input image vertical lock position - low (address 2ch) (r/w) it defines the low byte of the number of input lines where display image timing synchronizes the input image source. d7-0 ipv_lock_ pos[7:0] input image vertical lock position - high (address 2dh) (r/w) it defines the high byte of the number of input lines where display image timing synchronizes the input image source. d7-3 reserved d2-0 ipv_lock_ pos[10:8] input image horizontal lock position - low (address 2eh) (r/w) it defines the low byte of the number of input pixel clocks where display image timing synchronizes the input image source. d7-0 iph_lock_ pos[7:0] input image horizontal lock position - high (address 2fh) (r/w) it defines the high byte of the number of input pixel clocks where display image timing synchronizes the input image source. d7-3 reserved d2-0 iph_lock_ pos[10:8] auto calibration control 0 (address 30h) (r/w) d7 pixel grab ready flag (ro) 0: ready 1: not ready d6 pixel grab update enable 0: stop updating 1: continue updating d5 threshold select used in histogram mode or min/max mode. 0: high bound / max 1: low bound / min d4 phase calibration method select 0: myson proprietary method 1: difference value method d3-2 auto calibration modes select the measured value is available one item at a time, selected as shown: 00: phase calibration mode
myson technology MTL001 (rev. 0.95) revision 0.95 - 32 - 2000/06/14 01: histogram mode 10: min/max mode 11: pixel grab mode d1 auto calibration burst mode enable ( except pixel grab mode) 0: single mode 1: burst mode d0 auto calibration enable (w) ( except pixel grab value) 0: disable 1: enable auto calibr ation ready flag (r) 0: ready 1: not ready auto calibration control 1 (address 31h) (r/w) d7-3 reserved d2-0 mask lsbs of input image select it is used only for phase calibration to mask noise. 000: no mask 001: mask bit0 010: mask bit0 ,1 011: mask bit0 ,1,2 100: mask bit0 ,1,2,3 101: mask bit0 ,1,2,3,4 110: mask bit0 ,1,2,3,4,5 111: mask bit0 ,0,1,2,3,4,5,6 auto calibration red value - byte 0 (address 34h) (ro) it states the byte 0 of the number of phase calibration red value in one frame or the byte 0 of the number of histogram red value in one frame or the pixel grab red value in one frame of non_interlace mode or first field of interlace mode. d7-0 calval_ r[7:0] auto calibration red value - byte 1 (address 35h) (ro) it states the byte 1 of the number of phase calibration red value in one frame or the byte 1 of the number of histogram red value in one frame or the pixel grab green value in one frame of non_interlace mode or first field of interlace mode. d7-0 calval _ r[15:8] auto calibration red value - byte 2 (address 36h) (ro) it states the byte 2 of the number of phase calibration red value in one frame or the byte 2 of the number of histogram red value in one frame or the pixel grab blue value in one frame of non_interlace mode or first field of interlace mode. d7-0 calval_ r[23:16] auto calibration red value - byte 3 (address 37h) (ro)
myson technology MTL001 (rev. 0.95) revision 0.95 - 33 - 2000/06/14 it states the byte 3 of the number of phase calibration red value in one frame. d7-6 reserved d5-0 calval_ r[29:24] auto calibration green value - byte 0 (address 38h) (ro) it states the byte 0 of the number of phase calibration green value in one frame or the byte 0 of the number of histogram green value in one frame or the pixel grab red value in second field of interlace mode. d7-0 calval_ g[7:0] auto calibration green value - byte 1 (address 39h) (ro) it states the byte 1 of the number of phase calibration green value in one frame or the byte 1 of the number of histogram green value in one frame or the pixel grab green value in second field of interlace mode. d7-0 calval_ g[15:8] auto calibration green value - byte 2 (address 3ah) (ro) it states the byte 2 of the number of phase calibration green value in one frame or the byte 2 of the number of histogram green value in one frame or the pixel grab blue value in second field of interlace mode. d7-0 calval_ g[23:16] auto calibration green value - byte 3 (address 3bh) (ro) it states the byte 3 of the number of phase calibration green value in one frame. d7-6 reserved d5-0 calval_ g[29:24] auto calibration blue value - byte 0 (address 3ch) (ro) it states the byte 0 of the number of phase calibration blue value in one frame or the byte 0 of the number of histogram blue value in one frame or the min/max red value in one frame. d7-0 calval_ b[7:0] auto calibration blue value - byte 1 (address 3dh) (ro) it states the byte 1 of the number of phase calibration blue value in one frame or the byte 1 of the number of histogram blue value in one frame or the min/max green value in one frame. d7-0 calval_ b[15:8] auto calibration blue value - byte 2 (address 3eh) (ro)
myson technology MTL001 (rev. 0.95) revision 0.95 - 34 - 2000/06/14 it states the byte 2 of the number of phase calibration blue value in one frame or the byte 2 of the number of histogram blue value in one frame or the min/max blue value in one frame. d7-0 calval_ b[23:16] auto calibration blue value - byte 3 (address 3fh) (ro) it states the byte 3 of the number of phase calibration blue value in one frame. d7-6 reserved d5-0 calval _ b[29:24] pixel grab v reference position - low (address 40h) (r/w) it states the low byte of vertical reference position in pixel grab mode. d7-0 vgrab_ pos[7:0] pixel grab v reference position - high (address 41h) (r/w) it states the high byte of vertical reference position in pixel grab mode. d7-3 reserved d2-0 vgrab_ pos[10:8] pixel grab h reference position - low (address 42h) (r/w) it states the low byte of horizontal reference position in pixel grab mode. d7-0 hgrab_ pos[7:0] pixel grab h reference position - high (address 43h) (r/w) it states the high byte of horizontal reference position in pixel grab mode. d7-3 reserved d2-0 hgrab_ pos[10:8] histogram reference color - red (address 44h) (r/w) it states the histogram reference red color in histogram mode. d7-0 hist_ r[7:0] histogram reference color - green (address 45h) (r/w) it states the histogram reference green color in histogram mode. d7-0 hist_ g[7:0] histogram reference color - blue (address 46h) (r/w) it states the histogram reference blue color in histogram mode.
myson technology MTL001 (rev. 0.95) revision 0.95 - 35 - 2000/06/14 d7-0 hist_ b[7:0] sync processor control (address 48h) (r/w) d7-2 reserved d1-0 sync source 00: from h/v sync 01: from cvsync (composite sync) 1x: auto switch to cvsync when cvsync is present, but vsync not. auto position control (address 49h) (r/w) d7-2 reserved d1 auto position burst mode enable 0: single mode 1: burst mode d0 auto position enable (w) 0: disable 1: enable auto position ready flag (r) 0: ready 1: not ready auto position reference color - red (address 4ah) (r/w) it defines the red component color for selecting between black and non-black pixels. d7-0 ref_color_ red[7:0] auto position reference color - green (address 4bh) (r/w) it defines the green component color for selecting between black and non-black pixels. d7-0 ref_color_ green[7:0] auto position reference color - blue (address 4ch) (r/w) it defines the blue component color for selecting between black and non-black pixels. d7-0 ref_color_ blue[7:0] clamp pulse control 0 (address 4eh) (r/w) d7 clamp pulse mask 0: normal 1: mask out clamp pulse d6 clamp pulse start reference edge 0: from input hsync trailing edge. 1: from input hsync leading edge. d5 clamp pulse output polarity 0: active high
myson technology MTL001 (rev. 0.95) revision 0.95 - 36 - 2000/06/14 1: active low d4-0 clamp pulse start start of clamp pulse after the selected edge of input hsync by input dclk. clamp pulse control 1 (address 4fh) (r/w) d7-5 reserved d4-0 clamp pulse width to adjust clamp pulse width by input dclk. input vs period count by refclk - low (address 50h) (ro) it states the low byte of the number of refclk of the vertical sync period measurement. d7-0 vsprd[7:0] input vs period count by refclk - high (address 51h) (ro) it states the high byte of the number of refclk of the vertical sync period measurement. d7-4 reserved d3-0 vsprd[11:8] input v back porch count by input hs - low (address 52h) (ro) it states the low byte of the number of lines between the end of vsync and the active image. d7-0 vbpw[7:0] input v back porch count by input hs - high (address 53h) (ro) it states the high byte of the number of lines between the end of vsync and the active image d7-3 reserved d2-0 vbpw[10:8] input v active image count by input hs - low (address 54h) (ro) it states the low byte of the number of the active image lines. d7-0 vactw[7:0] input v active image count by input hs - high (address 55h) (ro) it states the high byte of the number of the active image lines d7-3 reserved d2-0 vactw[10:8] input v total image count by input hs - low (address 56h) (ro) it states the low byte of the number of the total image lines.
myson technology MTL001 (rev. 0.95) revision 0.95 - 37 - 2000/06/14 d7-0 vtotw[7:0] input v total image count by input hs - high (address 57h) (ro) it states the high byte of the number of the total image lines. d7-3 reserved d2-0 vtotw[10:8] input hs period count by refclk - low (address 58h) (ro) it states the low byte of the number of refclks of the horizontal sync period measurement. d7-0 hsprd[7:0] input hs period count by refclk - high (address 59h) (ro) it states the high byte of the number of refclks of the horizontal sync period measurement. d7-5 reserved d4-0 hsprd[12:8] input h back porch count by input pixel clock -low (address 5ah) (ro) it states the low byte of the number of pixels between the end of hsync and the active image. d7-0 hbpw[7:0] input h back porch count by input pixel clock -high (address 5bh) (ro) it states the high byte of the number of pixels between the end of hsync and the active image. d7-3 reserved d2-0 hbpw[10:8] input h active image count by input pixel clock-low(address 5ch) (ro) it states the low byte of the number of the horizontal active image pixels. d7-0 hactw[7:0] input h active image count by input pixel clock-high(address 5dh)(ro) it states the high byte of the number of the horizontal active image pixels. d7-3 reserved d2-0 hactw[10:8] input h total image count by input pixel clock- low (address 5eh) (ro) it states the low byte of the number of the horizontal total image pixels.
myson technology MTL001 (rev. 0.95) revision 0.95 - 38 - 2000/06/14 d7-0 htotw[7:0] input h total image count by input pixel clock- high (address 5fh) (ro) it states the high byte of the number of the horizontal total image pixels. d7-3 re served d2-0 htotw[10:8] display vertical total - low (address 60h) (r/w) it defines the low byte of the number of lines per display frame. d7-0 dv_ total[7:0] display vertical total - high (address 61h) (r/w) it defines the high byte of the number of lines per display frame. d7-3 reserved d2-0 dv_ total[10:8] display vertical sync end - low (address 62h) (r/w) it defines the low byte of vertical sync end position in lines. d7-0 dv_sync_ end[7:0] display vertical vsync end - high (address 63h) (r/w) it defines the high byte of vertical sync end position in lines. d7-3 reserved d2-0 dv_sync_ end[10:8] note: display vertical sync start is always equal 0. display vertical active start - low (address 64h) (r/w) it defines the low byte of vertical active region start position in lines. d7-0 dv_act_ start[7:0] display vertical active start - high (address 65h) (r/w) it defines the high byte of vertical active region start position in lines. d7-3 reserved d2-0 dv_act_ start[10:8] display vertical active end - low (address 66h) (r/w) it defines the low byte of vertical active region end position in lines.
myson technology MTL001 (rev. 0.95) revision 0.95 - 39 - 2000/06/14 d7-0 dv_act_ end[7:0] display vertical active end - high (address 67h) (r/w) it defines the high byte of vertical active region end position in lines. d7-3 reserved d2-0 dv_act_ end[10:8] display vertical border start - low (address 68h) (r/w) it defines the low byte of vertical border start position in lines. d7-0 dv_bor_ start[7:0] display vertical border start - high (address 69h) (r/w) it defines the high byte of vertical border start position in lines. d7-3 reserved d2-0 dv_bor_ start[10:8] display vertical border end - low (address 6ah) (r/w) it defines the low byte of vertical border end position in lines. d7-0 dv_bor_ end[7:0] display vertical border end - high (address 6bh) (r/w) it defines the high byte of vertical border end position in lines. d7-3 reserved d2-0 dv_bor_ end[10:8] display horizontal total - low (address 70h) (r/w) it defines the low byte of the number of display clock cycles per display line. d7-0 dh_ total[7:0] display horizontal total - high (address 71h) (r/w) it defines the high byte of the number of display clock cycles per display line. d7-3 reserved d2-0 dh_ total[10:8] display horizontal sync end - low (address 72h) (r/w) it defines the low byte of horizontal sync end position in display clock cycles.
myson technology MTL001 (rev. 0.95) revision 0.95 - 40 - 2000/06/14 d7-0 dh_sync_ end[7:0] display horizontal sync end - high (address 73h) (r/w) it defines the high byte of horizontal sync end position in display clock cycles. d7-3 reserved d2-0 dh_sync_ end[10:8] note: display horizontal sync start is always equal 0. display horizontal active start - low (address 74h) (r/w) it defines the low byte of horizontal active region start position in display clock cycles. d7-0 dh_act_ start[7:0] display horizontal active start - high (address 75h) (r/w) it defines the high byte of horizontal active region start position in display clock cycles. d7-3 reser ved d2-0 dh_act_ start[10:8] display horizontal active end - low (address 76h) (r/w) it defines the low byte of horizontal active region end position in display clock cycles. d7-0 dh_act_ end[7:0] display horizontal active end - high (address 77h) (r/w) it defines the high byte of horizontal active region end position in display clock cycles. d7-3 reserved d2-0 dh_act_ end[10:8] display horizontal border start - low (address 78h) (r/w) it defines the low byte of horizontal border start position in display clock cycles. d7-0 dh_bor_ start[7:0] display horizontal border start - high (address 79h) (r/w) it defines the high byte of horizontal border start position in display clock cycles. d7-3 reserved d2-0 dh_bor_ start[10:8] display horizontal border end - low (address 7ah) (r/w) it defines the low byte of horizontal border end position in display clock cycles.
myson technology MTL001 (rev. 0.95) revision 0.95 - 41 - 2000/06/14 d7-0 dh_bor_ end[7:0] display horizontal border end - high (address 7bh) (r/w) it defines the high byte of horizontal border end position in display clock cycles. d7-3 reserved d2-0 dh_bor_ end[10:8] output image control register 0 (address 88h) (r/w) d7-3 reserved d2 output pixel 18 bit rgb mode select 0: 24 bit rgb 1: 18 bit rgb d1 output dual pixel da ta exchange 0: normal 1: exchange d0 output dual pixel select 0: dual pixel 1: single pixel output image control register 1 (address 89h) (r/w) d7-6 reserved d5 rgb brightness control enable 0: disable 1: enable d4 rgb gain control e nable 0: disable 1: enable d3-2 reserved d1 border window function 0: off 1: on d0 output blank screen 0: normal 1: output pixel masked as black color output image control register 2 (address 8ah) (r/w) d7 reserved d6 temporal di thering enable 0: static dithering 1: temporal dithering
myson technology MTL001 (rev. 0.95) revision 0.95 - 42 - 2000/06/14 d5 dithering table r/w access enable 0: disable 1: enable d4 dithering enable 0: disable 1: enable d3 reserved d2 10 bit gamma table enable 0: 8 bit gamma table 1: 10 bit ga mma table d1 gamma table r/w access enable 0: disable 1: enable d0 gamma correction function 0: off 1: on color gain control - red (address 90h) (r/w) it can be used to adjust the gain of red component of the display image. d7-0 rgain[7:0] 0(00h) ~ x1(80h) ~ x1.992185( ffh) color gain control - green (address 91h) (r/w) it can be used to adjust the gain of green component of the display image. d7-0 ggain[7:0] 0(00h) ~ x1(80h) ~ x1.992185( ffh) color gain control - blue (address 92h) (r/w) it can be used to adjust the gain of blue component of the display image. d7-0 bgain[7:0] 0(00h) ~ x1(80h) ~ x1.992185( ffh) color brightness control - red (address 93h) (r/w) it can be used to adjust the brightness of red component of the display image. d7-0 rbright[7:0] -128(80h) ~ 0(00h) ~127(7fh) color brightness control - green (address 94h) (r/w) it can be used to adjust the brightness of green component of the display image. d7-0 gbright[7:0] -128(80h) ~ 0(0 0h) ~127(7fh)
myson technology MTL001 (rev. 0.95) revision 0.95 - 43 - 2000/06/14 color brightness control - blue (address 95h) (r/w) it can be used to adjust the brightness of blue component of the display image. d7-0 bbright[7:0] -128(80h) ~ 0(00h) ~127(7fh) border window color - red (address 96h) (r/w) when the display image is not expanded to full screen, it can be specified as the red component of the border color. d7-0 bcr[7:0] border window color - green (address 97h) (r/w) when the display image is not expanded to full screen, it can be specified as the green component of the border color. d7-0 bcg[7:0] border window color - blue (address 98h) (r/w) when the display image is not expanded to full screen, it can be specified as the blue component of the border color. d7-0 bcb[7:0] dithering table data port (address 9eh) (r/w) since the dithering table is downloadable, this data port is the entry address. d7-0 dither_ port[7:0] gamma table data port (address 9fh) (r/w) since the gamma table is downloadable, this data port is the entry address. d7-0 gamma_ port[7:0] osd control register 0 (address a0h) (r/w) d7 osd output clock select 0: from internal display dot clock 1: from internal display dot clock x 2 d6 osd output vs invert 0: normal 1: invert d5-4 reserved d3 os d function 0: off 1: on d2 osd intensity enable (for motorola)
myson technology MTL001 (rev. 0.95) revision 0.95 - 44 - 2000/06/14 0: disable 1: enable d1-0 osd type select 00: osdrgb = { r 0000000, g 0000000, b 0000000} 01: osdrgb = { rr 000000, gg 000000, bb 000000} 10: osdrgb = { rrrr 0000, gggg 0000, bbbb 0000} 11: osdrgb = { rrrrrrrr , gggggggg , bbbbbbbb } r = osdr, g = osdg, b = osdb osd control register 1 (address a1h) (r/w) d7 osd output hs invert 0: normal 1: invert. d6 osd output dclk invert 0: normal 1: invert. d5-4 osd output hs delay 4 steps t o change, each of them is 1ns delay/step. d3 osd input data sample clock invert 0: normal. 1: invert. d2-0 osd input data sample clock delay 8 steps to change, each of them is 1ns delay/step. osd control register 2 (address a2h) (r/w) d7-4 reserved d3-0 osd output clock delay 16 steps to change, each of them is 1ns delay/step. output invert control (address a4h) (r/w) d7 reserved d6 rgb data invert enable 0: disable 1: enable d5 display dclk2 invert 0: normal 1: inve rt d4 display dclk1 invert 0: normal 1: invert d3 reserved d2 display data enable (dden) invert 0: normal
myson technology MTL001 (rev. 0.95) revision 0.95 - 45 - 2000/06/14 1: invert d1 display vsync invert 0: normal 1: invert d0 display hsync invert 0: normal 1: invert output tri_state control (address a5h) (r/w) d7 display data r2out, g2out, b2out output disable 0: normal 1: tri_stated d6 display data r1out, g1out, b1out output disable 0: normal 1: tri_stated d5 display dclk2 output disable 0: normal 1: tri_stated d4 displ ay dclk1 output disable 0: normal 1: tri_stated d3 osd oclk / ovsync / ohsync output disable 0: normal 1: tri_stated d2 display data enable (dden) output disable 0: normal 1: tri_stated d1 display vsync output disable 0: normal 1: tri_stated d0 display hsync output disable 0: normal 1: tri_stated output clocks delay adjustment (address a6h) (r/w) d7-4 display dclk2 delay adjustment 16 steps to adjust, typical 1ns delay/step d3-0 display dclk1 delay adjustment 16 steps to adjust, typical 1ns delay/step output clocks duty cycle adjustment (address a7h) (r/w) d7 display dclk2 duty cycle increase/decrease 0: decrease 1: increase
myson technology MTL001 (rev. 0.95) revision 0.95 - 46 - 2000/06/14 d6-4 display dclk2 duty cycle adjustment 8 steps to adjust, typical 0.5ns delay/ste p d3 display dclk1 duty cycle increase/decrease 0: decrease 1: increase d2-0 display dclk1 duty cycle adjustment 8 steps to adjust, typical 0.5ns delay/step output miscellaneous control (address a9h) (r/w) d7 second field line buffer overflo w status for interlace input (ro) 0: not overflow 1: overflow d6 second field line buffer underflow status for interlace input (ro) 0: not underflow 1: underflow d5 first field line buffer overflow status for interlace input or line buffer overflow status for non-interlace input (ro) 0: not overflow 1: overflow d4 first field line buffer underflow status for interlace input or line buffer overflow status for non-interlace input (ro ) 0: not underflow 1: underflow d3 auto outp ut horizontal total calculation start (w) 0: disable 1: enable auto output horizontal total calculation ready flag (r) 0: ready 1: not ready d2-0 reserved output vertical active line number - low (address aah) (r/w) it defines the low byte of output vertical active line number only used for getting the values of reg. ach and adh . d7-0 ovde[7:0] output vertical active line number - high (address abh) (r/w) it defines the high byte of output vertical active line number only used for getting the values of reg. ach and adh . d1-0 ovde[9:8] output horizontal total pixel number - low (address ach) (ro) it states the low byte of output horizontal total pixel number.
myson technology MTL001 (rev. 0.95) revision 0.95 - 47 - 2000/06/14 d7-0 ohtot[7:0] output horizontal total pixel number - high (address adh) (ro) it states the high byte of output horizontal total pixel number. d2-0 ohtot[10:8] output horizontal total residue number - low (address aeh) (ro) it states the low byte of output horizontal total pixel residue number. d7-0 ohtot_ res[7:0] output horizontal total residue number - high (address afh) (ro) it states the high byte of output horizontal total pixel residue number. d7-2 reserved d1-0 ohtot_ res[9:8] zoom control register 0 (address b0h) (r/w) d7 vertical scale mode 0: scale up 1: scale down d6-4 vertical scale select 0xx: pass mode 10x: duplicate mode 110: bilinear mode 111: interpolation table mode (only for scale up) d3 horizontal scale mode 0: scale up 1: scale down d2-0 horizontal scale select 0xx: pass mode 10x: duplicate mode 110: bilinear mode 111: interpolation table mode zoom control register 1 (address b1h) (r/w) d7-1 reserved d0 interpolation table r/w access enable 0: disable 1: enable zoom vertical scale down integer ratio region (address b2h) (r/w) it defines vertical scale down integer ratio value region
myson technology MTL001 (rev. 0.95) revision 0.95 - 48 - 2000/06/14 d7-3 reserved d2-0 zvdiv[2:0] 0 : scale down ratio = 1-1/2(exclude 1) 1 : scale down ratio = 1/2-1/4(exclude 1/2) 2: scale down ratio = 1/4-1/8(exclu de 1/4) 3: scale down ratio = 1/8-1/16(exclude 1/8) 4: scale down ratio = 1/16-1/32(exclude 1/16) zoom horizontal scale down integer ratio region (address b3h) (r/w) it defines horizontal scale down integer ratio value region. d7-3 reserved d2-0 zhdiv[2:0] 0 : scale down ratio = 1-1/2(exclude 1) 1 : scale down ratio = 1/2-1/4(exclude 1/2) 2: scale down ratio = 1/4-1/8(exclude 1/4) 3: scale down ratio = 1/8-1/16(exclude 1/8) 4: scale down ratio = 1/16-1/32(exclude 1/16) zoom vertical scale ratio ? low (address b4h) (r/w) it defines the low byte of vertical scale ratio value for scale up and down. d7-0 zvsf[7:0] zoom vertical scale ratio - high (address b5h) (r/w) it defines the low byte of vertical scale ratio value for scale up and down. d7-0 zvsf[15:8] for scale up zvsf = ceil[( input_height ? 1)/ ( output_height ? 1)* 2 16 ] for scale down zvsf = ceil{[( input_height ? ? 1)/ ( output_height ? 1)-1]* 2 16 } ,where input_height ? = input_height / 2^zvdiv. the means of zvdiv is referenced to reg. b2h. zoom horizontal scale ratio - low (address b6h) (r/w) it defines the low byte of horizontal scale ratio value for scale up and down. d7-0 zhsf[7:0] zoom horizontal scale ratio - high (address b7h) (r/w) it defines the high byte of horizontal scale ratio value for scale up and down. d7-0 zhsf[15:8] for scale up zhsf = round[( input_width ? 1)/ ( output_width ? 1)* 2 16 ] for scale down zvsf = round{[( input_width ? ? 1)/ ( output_width ? 1)-1]* 2 16 } ,where input_width ? = input_width / 2^zhdiv. the means of zhdiv is referenced to reg. b3h. interpolation table data port (address bfh) (r/w) it defines the entry address of the interpolation table data port.
myson technology MTL001 (rev. 0.95) revision 0.95 - 49 - 2000/06/14 d7-0 tfport[7:0] host control register 0 (address c0h) (r/w) d7 ho st screen write stop enable (wo) 0: disable 1: enable d6-1 force to 001010 d0 host screen write start enable (w) 0: disable 1: enable host screen write ready flag (r) 0: ready 1: not ready host control register 1 (address c1h) (r/w) d7 reserved d6 i2c bus address no increment 0: normal 1: no increment d5 double buffer load select 0: immediately 1: delay to display vsync d4 registers double buffer function enable 0: disable 1: enable d3-2 reserved d1 display r egisters double buffer load (wo) d0 input registers double buffer load (wo) host screen write line length - low (address c4h) (r/w) it defines the low byte of the vertical line length for host screen write. d7-0 hs_ len[7:0] host screen write line length - high (address c5h) (r/w) it defines the high byte of the vertical line length for host screen write. d7-3 reserved d2-0 hs_ len[10:8] host fill red color (address c6h) (r/w) it defines fill red color for host screen write.
myson technology MTL001 (rev. 0.95) revision 0.95 - 50 - 2000/06/14 d7-0 hfr[7:0] host fill green color (address c7h) (r/w) it defines fill green color for host screen write. d7-0 hfg[7:0] host fill blue color (address c8h) (r/w) it defines fill blue color for host screen write. d7-0 hfb[7:0] host access mode status (address cbh) (ro) d7-1 reserved d0 host access mode 0: 2-wire serial mode (iic) 1: 8-bit parallel mode memory type control (address d0h) (r/w) it defines the memory type and size. d7-5 reserved d4 32 bits memory bus (only for x2 memory confi guration) 0: disable 1: enable d3 reserved d2-0 000: 16m sdram x 3 001: 16m sdram x 2 010: 8m sgram x 3 011: 8m sgram x 2 10x: reserved 110: 16m sgram x 3 111: 16m sgram x 2 memory self test control (address d2h) (r/w) it controls the operation of memory self test mode. d7- 3 reserved d2 memory self test mode result status (ro) 0: success 1: fail d1 memory self test mode finish status (ro) 0: finish 1: not finish
myson technology MTL001 (rev. 0.95) revision 0.95 - 51 - 2000/06/14 d0 memory self test mode enable 0: disable 1: enable memory line offset ? low (address d4h) (r/w) it defines the low byte of memory line offset address length for memory read/write. d7-0 line_ offset [7:0] memory line offset ? high (address d5h) (r/w) it defines the high byte of memory line offset address length for memory read/write. d7-3 reserved d2-0 line_ offset [10:8] memory self-test compare error address ? low (address dbh) (ro) it defines the low byte of memory base address for memory self-test comparing error report. d7-0 msftba [7 :0] memory self-test compare error address ? middle (address dch) (ro) it defines the middle byte of memory base address for memory self-test comparing error report. d7-0 msftba [15:8] memory self-test compare error address ? high (address ddh) (ro) it defines the high byte of memory base address for memory self-test comparing error report and patterns number. d7 reserved d6-5 memory self-test patterns number when comparing error 00: pattern constructed by linear memory address 01: 48 bits pa ttern toggled between 55 and aa 10: 48 bits pattern toggled between aa and 55 11: reserved d4-0 msftba [20:16] clock synthesizer control register (address e0h) (r/w) d7-4 reserved d3 memory clock source 0: internal memory clock 1: external m emory clock from pin extmclk d2 display clock source 0: internal display clock 1: external display clock from pin extdclk
myson technology MTL001 (rev. 0.95) revision 0.95 - 52 - 2000/06/14 d1 memory clock synthesizer enable 0: enable 1: disable d0 display clock synthesizer enable 0: enable 1: disable clock synthesizer value load (address e1h) (wo) d7-2 reserved d1 memory clock synthesizer value load (wo) d0 display clock synthesizer value load ( wo) display clock synthesizer n value (address e2h) (r/w) d7-0 display clock synthesizer n value display clock synthesizer m value (address e3h) (r/w) d7-0 display clock synthesizer m value memory clock synthesizer n value (address e4h) (r/w) d7-0 memory clock synthesizer n value memory clock synthesizer m value (address e5h) (r/w) d7-0 memory clock synthesizer m value clock synthesizer r value (address e6h) (r/w) d7-4 reserved d3-2 memory clock synthesizer r value 00: no divided 01: divided by 2 1x: divided by 4 d1-0 display clock synthesizer r value 00: no divided 01: divided by 2 1x: divided by 4 sync interrupt flag control (address e8h) (r) it contains the status of sync interrupts. d7 display vsync pulse interrupt status 0: no display vsync pulse detected 1: any display vsync pulse detec ted d6 input vsync pulse interrupt status 0: no input vsync pulse detected 1: any input vsync pulse detected
myson technology MTL001 (rev. 0.95) revision 0.95 - 53 - 2000/06/14 d5 vsync presence change status 0: no change 1: change d4 hsync presence change status 0: no change 1: change d3 vsync polarity change status 0: no change 1: change d2 hsync polarity change status 0: no change 1: change d1 vsync frequency change status 0: no change 1: change d0 hsync frequency change status 0: no change 1: change sync interrupt flag control (address e8h) (w) it is used to clear the corresponding sync interrupt signal when software finishes serving the interrupt service routine. d7 clear display vsync pulse interrupt enable 0: disable 1: enable d6 clear input vsync pulse interrupt e nable 0: disable 1: enable d5 clear vsync presence change interrupt enable 0: disable 1: enable d4 clear hsync presence change interrupt enable 0: disable 1: enable d3 clear vsync polarity change interrupt enable 0: disable 1: enable d2 clear hsync polarity change interrupt enable 0: disable 1: enable d1 clear vsync frequency change interrupt enable 0: disable 1: enable
myson technology MTL001 (rev. 0.95) revision 0.95 - 54 - 2000/06/14 d0 clear hsync frequency change interrupt enable 0: disable 1: enable general interrupt flag control (address e9h) (r) it contains the status of general interrupts. d7-2 reserved d1 auto position finish status (valid for single mode only) 0: not finish 1: finish d0 auto calibration finish status (valid for single mode only) 0: not finish 1: finish general interrupt flag control (address e9h) (w) it is used to clear the corresponding general interrupt signal when software finishes serving the interrupt service routine. d7-2 reserved d1 clear auto position finish interrupt enable 0: disable 1: enable d0 clear auto calibration finish interrupt enable 0: disable 1: enable sync interrupt flag enable (address eah) (r/w) it is used to enable sync interrupt function. d7 display vsync pulse interrupt enable 0: disable 1: enable d6 input vsync pulse interrupt enable 0: disable 1: enable d5 vsync presence change interrupt enable 0: disable 1: enable d4 hsync presence change interrupt enable 0: disable 1: enable d3 vsync polarity change interrupt enabl e 0: disable 1: enable
myson technology MTL001 (rev. 0.95) revision 0.95 - 55 - 2000/06/14 d2 hsync polarity change interrupt enable 0: disable 1: enable d1 vsync frequency change interrupt enable 0: disable 1: enable d0 hsync frequency change interrupt enable 0: disable 1: enable general interrupt flag enable (address ebh) (r/w) it is used to enable general interrupt functions. d7 interrupt output polarity invert 0: active low 1: active high d6-2 reserved d1 auto position finish interrupt enable 0: disable 1: enable d0 auto calibra tion finish interrupt enable 0: disable 1: enable hs frequency change interrupt compare (address ech) (r/w) it is used to control interrupt generation by comparing the frequency change value when input hs frequency changes. d7-0 hscmpreg[7:0] power management control (address f1h) (r/w) d7 reserved d6 power down gamma & interpolation table 0: normal 1: power down d5 power down output line buffers 0: normal 1: power down d4 power down input line buffers 0: normal 1: power do wn d3-2 reserved d1 power down all the clocks except refclk 0: normal
myson technology MTL001 (rev. 0.95) revision 0.95 - 56 - 2000/06/14 1: power down d0 software reset enable 0: disable 1: enable gpio control register (address f4h) (r/w) it controls the data of the gpio pins. d7-0 gpio[7:0] gpio direction control (address f5h) (r/w) it controls the in/out direction of the gpio pins, where ? 0 ? means output, and ? 1 ? means tri_state or input. d7-6 gpio[7:6] output enable 0: output 1: tri_state d5-0 gpio[5:0] in/out select 0: output 1: input gpio misc control (address f6h) (r/w) it defines the gpio pins miscellaneous control. d7-1 reserved d0 gpio[7:6] output pins source 0: from reg. f4h/d7-6 1: from advs/adhs
myson technology MTL001 (rev. 0.95) revision 0.95 - 57 - 2000/06/14 5. electrical characteristics 5.1 dc characteristics table 5.1 recommended operating conditions symbol parameter min typ max unit vcc operation voltage 3.0 3.3 3.6 v tamb operating ambient temperature 0 70 o c tstg storage temperature -55 150 o c table 5.2 dc electrical characteristics for 3.3 v operation symbol parameter conditions min typ max unit vil input low voltage 0.8 v vih input high voltage 2.0 v vt- input schmitt trigger low voltage at pins sda and sck 1.0 vt+ input schmitt trigger high voltage at pins sda and sck 1.7 vol output low voltage 0.4 v voh output high voltage 2.4 v ri input pull-up/down resistance vil = 0v or vih = vcc 75 kohm ili input leakage current -10 10 ua ilo output leakage current -20 20 ua
myson technology MTL001 (rev. 0.95) revision 0.95 - 58 - 2000/06/14 5.2 ac characteristics input interface timing figure 5.2.1 input interface timing table 5.2.1 input interface timing symbol parameter min max unit tids input image signal setup time for ipclk 2 ns tidh input image signal hold time for ipclk 3 ns tivhs input vsync/hsync setup time for ipclk 2 ns tivhh input vsync/hsync hold time for ipclk 3 ns tids tidh tivhh tivhs ipclk input vs/hs pixin[23:0]
myson technology MTL001 (rev. 0.95) revision 0.95 - 59 - 2000/06/14 output interface timing figure 5.2.2 output interface timing table 5.2.2 output interface timing symbol parameter min max unit tdck display clock ddclk frequency 10 ns tdvs display vsync output delay to ddclk 2 ns tdhs display hsync output delay to ddclk 0.5 ns tdde display dden output delay to ddclk 1 ns tddp display data output delay to ddclk 1.5 ns note: ddclk phase can be adjusted relative to data and control outputs using the ddclk_inv (reg. a4h/d5-4) and ddclk_ delay[2:0] (reg. a6h/d7-0) programming controls. k tdde tdhs tddp tdvs ddclk display vs pixout1[23:0] / pixout2[23:0] display hs display dden
myson technology MTL001 (rev. 0.95) revision 0.95 - 60 - 2000/06/14 osd interface timing figure 5.2.3 osd interface timing table 5.2.3 osd interface timing symbol parameter min max unit tosdd osd vs / hs output delay to oclk 2 ns tosds osd signal input setup time for oclk 5.5 ns tosdh osd signal input hold time for oclk 0 ns note: oclk phase can be adjusted using oclk_inv (reg. a1h/d3) programming control and ohsync phase can be adjusted using ohsync_delay[1:0] (reg. a1h/d5-4) programming control. tosdd tosds tosdh oclk input osdden / osdred / osdgrn / osdblu ovsync / ohsync
myson technology MTL001 (rev. 0.95) revision 0.95 - 61 - 2000/06/14 i2c host interface timing figure 5.2.4 i2c host interface timing table 5.2.4 i2c host interface timing symbol parameter min max unit thigh clock high period 500 ns tlow clock low period 500 ns tsu:dat data in setup time 200 ns thd:dat data in hold time 100 ns tsu:sta start condition setup time 500 ns thd:sta start condition hold time 500 ns tsu:sto stop condition setup time 500 ns thd:sto stop condition hold time 500 ns tsu:dat thd:dat tsu:sta thd:sto tsu:sto thd:sta tlow thigh
myson technology MTL001 (rev. 0.95) revision 0.95 - 62 - 2000/06/14 8-bit direct host interface timing figure 5.2.5 8-bit direct host interface timing table 5.2.5 8-bit direct host interface timing symbol parameter min max unit tavll address valid to ale low 3 ns tllax address hold after ale low 5 ns trwpw wr/rd pulse width 35 ns tllwl ale low to wr/rd low 5 ns tqvwh data valid to wr high 3 ns twhqx data hold after wr 10 ns twhlh wr/rd high to ale high 0 ns trlaz rd low to address float -5 ns trldv rd low to valid data in 30 ns trhdz data float after rd high 0 15 ns tqvwh data in data out a0-a7 a0-a7 tavll tllax tllwl trwpw twhlh trhdz trldv h h h trlaz ad(7:0)/wr ad(7:0)/rd ale wr/rd
myson technology MTL001 (rev. 0.95) revision 0.95 - 63 - 2000/06/14 memory interface (sdram/sgram) timing figure 5.2.6 memory interface timing table 5.2.6 memory interface timing symbol parameter min max unit t mck memory clock cycle time 8.5 ns t mch / tmck memory clock duty cycle 0.4 0.6 ns t mds data-in setup time for mck 1 ns tmdh data-in hold time for mck 2 ns tm od memory output delay to mck 2 8.5 ns mcke, mcs#, mras#, mcas#, mwe#, dqm[1:0], ma[11:0] t mch t mck t m od t mds t mdh m ck md[47:0]
myson technology MTL001 (rev. 0.95) revision 0.95 - 64 - 2000/06/14 aaa bbb seating plane 6. package dimension 120/128/132/144/160/184/208/256l ofp 28 x 28 x 3.32 mm 2.6mm footprint a2 gage plane c 3 1 c ccc d a-b c ddd b e 4x a- b d h a- b d c 4x e e e1 e2 d1 d2 d millimeter inch symbol min. nom. max . min. nom. max. a x x 4.10 x x 0.161 a1 0.25 x x 0.010 x x a2 3.20 3.32 3.60 0.126 0.131 0.142 d 30.60 bsc 1.205 bsc d1 28.00 bsc 1.102 bsc e 30.60 bsc 1.205 bsc e1 28.00 bsc 1.102 bsc r2 0.08 x 0.25 0.003 x 0.010 r1 0.08 x 0.003 x x 0 3.5 7 0 3.5 7 1 0 x x 0 x x 2 8 ref 8 ref 3 8 ref 8 ref c 0.09 0.15 0.20 0.004 0.005 0.008 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.30 0.051 ref s 0.20 x x 0.008 x x notes: 1. dimensions d1 and e1 do not include mold protrusion. 2. simension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. dambar can not be located on the lower radius or the foot. the minimum space between protrusion and an adjacent lead shall not be less than 0.07 mm. 3. the top package booy size may be smaller than the bottom package booy size. min. nom. max. min. nom. max. 0.13 0.16 0.23 0.005 0.006 0.009 0.40 bsc. 0.016 bsc. 25.20 0.992 25.20 0.992 tolerances of form and position 0.20 0.008 0.20 0.008 x 0.08 x x 0.003 x x 0.07 x x 0.003 x b a m s s s 2 l 0.25mm r1 r2 0.05 c ;l1 s a1

▲Up To Search▲

Price & Availability of MTL001

	To Download MTL001 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .